This invention relates to an integrated circuits, and more particularly to an integrated circuit device with high quality factor (Q) metal-insulator-metal (MIM) capacitor and its forming process.
In current very large scale integration (VLSI) such as dynamic random access memory (DRAM), the capacitor is used as a storage element to store digital data. Writing digital data is performed by the steps of charging and discharging the capacitor. In current VLSI technology, double polysilicon capacitor (DPC) are widely used as the capacitor of VLSI.
Nowadays most digital and analog circuits are manufactured with VLSI technology, only the application of radio frequency (RF) is still not performed by VLSI technology. From 1990, the applications of radio frequency are developed gradually. They are applied to personal communications, radio communications, satellite communications, and radio peripheral equipment of computers. These applications are performed by monolithic microwave integrated circuit (MMIC) technology.
In MMIC design, the capacitor is made of metal-insulator-metal (MIM) such that the capacitor has higher capacitance. The MIM capacitor includes two metal conducting plates and a dielectric layer for separating the two metal conducting plates.
However, most capacitors are conventionally made by using polysilicon layers as upper and lower electrodes. For high frequency and RF applications, the electrodes made of polysilicon layers would result in a poor Q due to high resistivity of polysilicon material.
Therefore, the present invention provides a process for forming an integrated circuit device with high Q MIM capacitor.
It is an object of the present invention to provide an integrated circuit device with high Q MIM capacitor, wherein the material of dielectric layer of MIM capacitor is an anti-reflection coating (ARC).
It is another object of the present invention to provide a process for forming an integrated circuit device with high Q MIM capacitor.
In accordance with an aspect of the present invention, the integrated circuit device includes a semiconductor device, a first dielectric layer, a first barrier layer, a capacitor, an inter-metal dielectric layer, and a metal layer. The semiconductor device has plural semiconductor elements. The first dielectric layer is formed on the semiconductor device. The first barrier layer is formed on a portion of the first dielectric layer. The capacitor is formed on the first barrier layer and has a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the capacitor dielectric layer is made of anti-reflection coating (ARC) with relatively high dielectric constant. The inter-metal dielectric layer is formed on the capacitor and the first dielectric layer. The metal layer is formed on the inter-metal dielectric layer and used as conductive wires.
The semiconductor device includes a semiconductor substrate and a field oxide layer formed on the semiconductor substrate for defining an active area and an isolated area of the semiconductor substrate to isolate each of the semiconductor elements.
Preferably, the material of the semiconductor substrate is silicon or galium arsenide.
Preferably, the material of the first dielectric layer is borophosphosilicate glass (BPSG), the material of the first barrier layer is titanium nitride (TiN), the thickness of the first barrier layer is ranged from 200-1000 angstrom, the material of the lower electrode tungsten or aluminum, and the thickness of the lower electrode is ranged from 5000-10000 angstrom.
Preferably, the anti-reflection coating (ARC) is silicon-oxy-nitride (SiOxNy).
Preferably, the thickness of the capacitor dielectric layer is less than 10 nanometer, the material of the upper electrode is aluminum, and the material of the inter-metal dielectric layer is borophosphosilicate glass (BPSG) or silicon dioxide.
The integrated circuit device further includes plural plugs formed in the inter-metal dielectric layer for connecting the metal layer with one of the upper electrode and the lower electrode, respectively.
Preferably, the plural plugs are made of tungsten.
The integrated circuit device further includes a second barrier layer formed between portions of the inter-metal dielectric layer and the metal layer.
Preferably, the material of the second barrier layer is titanium nitride (TiN).
Preferably, the material of the metal layer is aluminum.
In accordance with another aspect of the present invention, the process for forming an integrated circuit device includes steps of forming a first barrier layer, forming a first metal layer, forming a second dielectric layer, forming a second metal layer, forming an upper electrode, forming a lower electrode, forming an inter-metal dielectric layer, forming plural plugs, forming a second barrier layer, forming a third metal layer, and removing a portion of the third metal layer and the second barrier layer thereby exposing a portion of the inter-metal dielectric layer. The first barrier layer is formed on a semiconductor device. The first metal layer is formed on the first barrier layer. The second dielectric layer is formed on the first metal layer and made of anti-reflection coating (ARC) with relatively high dielectric constant. The second metal layer is formed on the second dielectric layer. The upper electrode is formed by removing a portion of the second metal layer and the second dielectric layer thereby exposing a portion of the first metal layer. The lower electrode is formed by removing a portion of the first metal layer and the first barrier layer thereby exposing a portion of the semiconductor device. The inter-metal dielectric layer is formed on the upper electrode, the lower electrode and the semiconductor device. The plural plugs are formed in the inter-metal dielectric layer for connecting a third metal layer with the upper electrode or the lower electrode. The second barrier layer is formed on the inter-metal dielectric layer. The third metal layer is formed on the second barrier layer.
The semiconductor device is formed by the steps of providing a semiconductor substrate, forming a field oxide layer on the semiconductor substrate to define an active area and an isolated area of the semiconductor substrate, and forming a first dielectric layer on the field oxide layer and the semiconductor substrate.
Preferably, the first dielectric layer is formed by chemical vapor deposition (CVD) and then planarization process.
Preferably, the planarization process is performed by spin-on glass with back etch process or chemical mechanical polishing (CMP) process.
Preferably, the first barrier layer is formed by sputtering.
Preferably, the first metal layer is formed by chemical vapor deposition (CVD) process or sputtering.
The step of forming the upper electrode is performed by using a first photomask to pattern and etch the second metal layer and the second dielectric layer.
Preferably, the step of etching the second metal layer and the second dielectric layer is performed by dry etch.
Preferably, the dry etch is a reactive ion etch (RIE).
The step of forming the lower electrode is performed by using a second photomask to pattern and etch the first metal layer and the first barrier layer.
Preferably, the step of etching the first metal layer and the first barrier layer is performed by dry etch.
Preferably, the dry etch is a reactive ion etch (RIE).
Preferably, the inter-metal dielectric layer is formed by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).
The plural plugs are formed by the steps of patterning the intermetal dielectric layer by photolithography process to define a pattern connecting the third metal layer with the upper electrode or the lower electrode, forming plural via holes in the inter-metal dielectric layer according to the pattern, and filing the plural via holes with a metal material.
Preferably, the step of forming the plural via holes is performed by dry etch.
Preferably, the dry etch is a reactive ion etch (RIE).
Preferably, the metal material is tungsten.
Preferably, the third metal layer is formed by sputtering.
The step of removing a portion of the third metal layer and the second barrier layer thereby exposing a portion of the inter-metal dielectric layer is performed by using a fourth photomask to pattern and etch the third metal layer and the second barrier layer.